the entire AI optical buildout depends on a test step almost nobody can run at scale. 1/ silicon photonics moves data using light instead of electrical signals. optical chips follow the same test stages as any chip: wafer test, burn-in, package test. but testing light requires purpose-built equipment most test houses don't own. 2/ burn-in power is the other problem. newer silicon photonics devices can need 2-4x more power per wafer than earlier generations. that's a lot of energy to deliver across thousands of tiny photonic devices simultaneously. most facilities aren't built for it. 3/ co-packaged optics (CPO) makes wafer-level burn-in mandatory. once an optical chip is bonded into a switch package, you can't pull it out. a late failure means scrapping the whole switch. the economics f
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